Power Semiconductor Devices

1. Power Diodes

Basic Characteristics

Forward Voltage Drop: \[ V_F = V_{F0} + r_F \cdot I_F \]

where \(V_{F0}\) is threshold voltage, \(r_F\) is dynamic resistance

Peak Reverse Recovery Current: \[ I_{RR} = \sqrt{2 Q_{RR} \cdot \frac{dI_F}{dt}} \]

Reverse Recovery Time: \[ t_{rr} = t_s + t_f \]

where \(t_s\) is storage time, \(t_f\) is fall time

Key Facts:

Power diodes can handle currents from 1 A to several kA
Voltage ratings: 50 V to 10 kV
Junction temperature typically: 125°C to 150°C
Softness factor \(S = t_f / t_{rr}\) indicates recovery characteristics

Types of Power Diodes

Schottky Diode

Low forward voltage drop (0.3-0.5 V)
Fast switching, negligible \(t_{rr}\)
Low voltage applications (< 200 V)
Higher leakage current

Fast Recovery Diode

Reverse recovery time: 1-5 μs
Medium voltage applications
Used in converters and inverters

2. Thyristors (SCR)

Fundamental Relations

Two-Transistor Model Condition: \[ \alpha_1 + \alpha_2 \geq 1 \]

where \(\alpha_1\), \(\alpha_2\) are current gains of NPN and PNP sections

Latching Current: \[ I_L = \frac{1 - \alpha_1 - \alpha_2}{\alpha_1 \alpha_2} \cdot I_{C0} \]

Critical Rate of Rise of Current: \[ \left(\frac{di}{dt}\right)_{crit} = \frac{I_T}{t_{on}} \]

Critical Rate of Rise of Voltage: \[ \left(\frac{dv}{dt}\right)_{crit} = \frac{V_{DRM}}{t_{on}} \]

Important Parameters:

Holding Current \(I_H\): Minimum anode current to maintain conduction (typically 5-50 mA)
Latching Current \(I_L\): Minimum anode current to turn ON (typically 20-200 mA)
Turn-on time: 1-5 μs
Turn-off time: 5-100 μs
Voltage ratings: up to 12 kV
Current ratings: up to 5 kA

Commutation Methods

Natural Commutation: AC circuits where current naturally goes through zero
Forced Commutation: Using external circuits (LC circuits) to force current to zero

3. TRIAC (Triode AC Switch)

Power Control (Phase Angle): \[ P_{load} = \frac{V_m I_m}{2\pi} \left[\pi - \alpha + \frac{\sin(2\alpha)}{2}\right] \]

where \(\alpha\) is firing angle

RMS Current: \[ I_{rms} = I_m \sqrt{\frac{1}{2\pi}\left(\pi - \alpha + \frac{\sin(2\alpha)}{2}\right)} \]

TRIAC Characteristics:

Bidirectional thyristor - conducts in both directions
Three terminals: MT1, MT2, Gate
Four triggering modes based on gate and MT2 polarity
Typical voltage ratings: 400-800 V
Current ratings: 1-40 A (RMS)
Used in AC phase control and dimmer circuits

4. Power MOSFET

Fundamental Equations

Drain Current (Linear Region): \[ I_D = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right] \]

Drain Current (Saturation Region): \[ I_D = \frac{\mu_n C_{ox}}{2} \frac{W}{L} (V_{GS} - V_{th})^2 \]

ON-State Resistance: \[ R_{DS(on)} = \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{th})} \]

Switching Losses: \[ P_{sw} = \frac{1}{6}V_{DS} I_D (t_{on} + t_{off}) f_{sw} \]

Conduction Losses: \[ P_{cond} = I_{D(rms)}^2 \cdot R_{DS(on)} \]

Key Characteristics:

Voltage-controlled device: High input impedance (> 10⁹ Ω)
Fast switching speeds: 10-100 ns
No secondary breakdown
Positive temperature coefficient of \(R_{DS(on)}\) aids current sharing
Body diode provides reverse current path
Gate threshold voltage \(V_{th}\): 2-4 V typically
Maximum gate-source voltage: ±20 V

Parasitic Capacitances

Input Capacitance: \[ C_{iss} = C_{GS} + C_{GD} \]

Output Capacitance: \[ C_{oss} = C_{DS} + C_{GD} \]

Reverse Transfer Capacitance: \[ C_{rss} = C_{GD} \text{ (Miller capacitance)} \]

5. Insulated Gate Bipolar Transistor (IGBT)

Device Equations

Collector Current: \[ I_C = g_m (V_{GE} - V_{th}) \]

where \(g_m\) is transconductance

Saturation Voltage: \[ V_{CE(sat)} = V_{J1} + (I_C \cdot r_{drift}) + V_{J2} \]

Junction drops + drift region resistance drop

Total Losses: \[ P_{total} = V_{CE(sat)} \cdot I_C \cdot D + \frac{1}{6}V_{CE} I_C (t_{on} + t_{off}) f_{sw} \]

where \(D\) is duty cycle

IGBT Features:

Combines advantages of MOSFET and BJT
High input impedance like MOSFET
Low on-state voltage drop like BJT
Voltage ratings: 600 V to 6.5 kV
Current ratings: 10 A to 3.6 kA
Switching frequency: 1-50 kHz
Gate threshold voltage: 3-6 V
Tail current during turn-off due to minority carriers

Types of IGBTs

Punch-Through (PT) IGBT

Lower on-state voltage
Faster switching
More complex manufacturing
Used in high-frequency applications

Non Punch-Through (NPT) IGBT

Higher voltage blocking
Better ruggedness
Simpler manufacturing
Used in high-power applications

6. Gate Turn-Off Thyristor (GTO)

Turn-off Gain: \[ \beta_{off} = \frac{I_A}{I_G} \]

Typically 3-5 (much lower than turn-on gain)

Maximum Controllable Current: \[ I_{A(max)} = \beta_{off} \cdot I_{G(max)} \]

GTO Characteristics:

Can be turned ON and OFF by gate signal
Requires large negative gate current for turn-off (hundreds of amperes)
Turn-on gain: 20-100
Turn-off gain: 3-5
Voltage ratings: up to 6 kV
Current ratings: up to 4 kA
Used in high-power traction and industrial drives
Snubber circuits essential for dv/dt and di/dt protection

7. Power Bipolar Junction Transistor (BJT)

Collector Current (Active Region): \[ I_C = \beta I_B = h_{FE} I_B \]

Saturation Voltage: \[ V_{CE(sat)} \approx 0.2 \text{ to } 2 \text{ V} \]

Base Drive Requirement (Saturation): \[ I_B = \frac{I_C}{\beta_{forced}} \]

where \(\beta_{forced}\) = 5-10 (overdriven condition)

Storage Time: \[ t_s = \tau_b \ln\left(\frac{I_{B1} + I_{B2}}{I_{B2}}\right) \]

where \(\tau_b\) is base lifetime constant

Power BJT Characteristics:

Current-controlled device
Lower input impedance compared to MOSFET/IGBT
Requires continuous base current
Susceptible to secondary breakdown
Negative temperature coefficient (hot spots possible)
Storage time limits switching speed
Being replaced by MOSFETs and IGBTs in most applications

8. Thermal Analysis

Junction Temperature: \[ T_J = T_A + P_D \cdot \theta_{JA} \]

where \(\theta_{JA}\) is junction-to-ambient thermal resistance

Thermal Resistance Chain: \[ \theta_{JA} = \theta_{JC} + \theta_{CS} + \theta_{SA} \]

Junction-Case + Case-Sink + Sink-Ambient

Heat Sink Design: \[ \theta_{SA} = \frac{T_{J(max)} - T_A}{P_D} - \theta_{JC} - \theta_{CS} \]

Thermal Management:

Maximum junction temperature: 125-175°C (device dependent)
Typical \(\theta_{JC}\): 0.1-1 °C/W
Thermal interface material (TIM) improves \(\theta_{CS}\)
Forced air cooling reduces \(\theta_{SA}\) significantly
Transient thermal impedance: \(Z_{thJC}(t)\) used for pulse operations

9. Device Comparison

Parameter	Power MOSFET	IGBT	Thyristor	GTO
Control Type	Voltage	Voltage	Current	Current
Voltage Rating	Up to 1 kV	Up to 6.5 kV	Up to 12 kV	Up to 6 kV
Current Rating	Up to 200 A	Up to 3.6 kA	Up to 5 kA	Up to 4 kA
Switching Speed	10-100 ns	0.1-1 μs	10-100 μs	5-50 μs
On-State Drop	Higher (I²R)	Lower (1-3 V)	Lowest (1-2 V)	Low (2-3 V)
Gate Drive	Simple	Simple	Simple (ON only)	Complex
Frequency Range	Up to 1 MHz	Up to 50 kHz	Up to 1 kHz	Up to 10 kHz
Applications	SMPS, DC-DC	Motor drives, UPS	HVDC, phase control	Traction, drives

10. Safe Operating Area (SOA)

SOA Limits:

Maximum Current Limit: Device current rating
Maximum Voltage Limit: Device voltage rating (BVDSS, VCES, etc.)
Maximum Power Dissipation: \(P_{max} = (T_{J(max)} - T_C)/\theta_{JC}\)
Secondary Breakdown Limit: (BJT specific)

Forward Bias SOA (FBSOA):

Operating region during ON-state - limited by junction temperature

Reverse Bias SOA (RBSOA):

Operating region during turn-off - limited by avalanche energy

11. Protection Schemes

Overvoltage Protection

Snubber Capacitor: \[ C_s = \frac{I_L \cdot t_{off}}{V_{DS} - V_{DC}} \]

Clamping Voltage (Zener/TVS): \[ V_{clamp} = V_Z + I_{peak} \cdot R_Z \]

Overcurrent Protection

Methods:

Current sensing resistor (shunt)
Current transformer (CT)
Hall effect sensors
DESAT (desaturation) detection for IGBTs

Gate Protection

Techniques:

Zener diodes across gate-source
Gate resistor to limit di/dt
RC snubber for dv/dt protection
Isolated gate drivers for noise immunity

12. Snubber Circuits

Turn-Off Snubber (RC Snubber)

Capacitor Value: \[ C_s = \frac{t_{off} \cdot I_L}{2 \cdot \Delta V} \]

Resistor Value: \[ R_s = 2\sqrt{\frac{L_{stray}}{C_s}} \]

For critical damping

Snubber Energy Dissipation: \[ E_s = \frac{1}{2} C_s V_{DC}^2 \] \[ P_s = E_s \cdot f_{sw} \]

Turn-On Snubber (RL/Diode Snubber)

Inductor Value: \[ L_s = \frac{V_{DC} \cdot t_{on}}{2 \cdot \Delta I} \]

Snubber Design Guidelines:

Turn-off snubber limits dv/dt across device
Turn-on snubber limits di/dt through device
Stray inductance typically 50-200 nH in power circuits
Snubber components must be rated for high frequency
Film capacitors preferred over ceramic for snubbers

13. Gate Drive Requirements

MOSFET/IGBT Gate Drive

Gate Charge: \[ Q_g = Q_{gs} + Q_{gd} + Q_{plateau} \]

Gate Driver Current: \[ I_g = \frac{Q_g}{t_{drive}} \]

Gate Drive Power: \[ P_{gate} = Q_g \cdot V_{GS} \cdot f_{sw} \]

Miller Plateau Duration: \[ t_{plateau} = \frac{Q_{gd}}{I_g} = \frac{C_{gd} \cdot V_{DS}}{I_g} \]

Gate Resistor Selection

Turn-On Resistor: \[ R_{g(on)} = \frac{V_{driver} - V_{th}}{I_{g(desired)}} \]

Switching Time with Gate Resistor: \[ t_{rise} \approx 2.2 \cdot R_g \cdot C_{iss} \]

Gate Drive Best Practices:

Use low impedance gate drive (< 10 Ω typically)
Separate turn-on and turn-off resistors for optimization
Negative voltage for turn-off (-5 V to -15 V) prevents false triggering
Keep gate loop inductance < 20 nH
Use isolated gate drivers for high-side switches
Bootstrap circuits for half-bridge configurations

14. Series and Parallel Operation

Series Connection

Voltage Sharing Factor: \[ \alpha = \frac{V_1 / V_2}{1 + \Delta V_{th}/V_{nom}} \]

Static Voltage Sharing: \[ R_{share} \geq \frac{n \cdot V_{leak(max)}}{I_{leak(min)}} \]

where n is number of devices

Dynamic Voltage Sharing: \[ C_{share} = \frac{Q_{rr(max)} - Q_{rr(min)}}{\Delta V_{allow}} \]

Parallel Connection

Current Sharing (Static): \[ \frac{I_1}{I_2} = \frac{R_{DS(on)2}}{R_{DS(on)1}} \]

Source Inductance for Current Balance: \[ L_s \geq \frac{\Delta V_{th}}{di/dt} \]

Series/Parallel Operation Tips:

Match devices from same manufacturing batch
Series: Use voltage sharing capacitors and resistors
Parallel: Match gate drive delays within 10 ns
Parallel MOSFETs: Positive temp coefficient aids current sharing
Keep source/emitter leads short and equal length
Use symmetrical PCB layout

15. Switching Transitions

MOSFET Turn-On Process

Turn-On Stages:

Stage 1 (Delay): Gate charges to threshold \(V_{th}\), duration \(t_d\)
Stage 2 (Rise): Drain current rises, duration \(t_r\)
Stage 3 (Miller): Voltage falls at constant current, duration \(t_{fv}\)
Stage 4: Gate charges to final value

Turn-On Delay Time: \[ t_{d(on)} = R_g C_{iss} \ln\left(\frac{V_{driver}}{V_{driver} - V_{th}}\right) \]

Current Rise Time: \[ t_r = \frac{Q_{gs2} - Q_{gs1}}{I_g} \]

Voltage Fall Time: \[ t_{fv} = \frac{Q_{gd}}{I_g} = \frac{C_{gd} \cdot V_{DS}}{I_g} \]

Turn-Off Process

Turn-Off Delay Time: \[ t_{d(off)} = R_g C_{iss} \ln\left(\frac{V_{GS(on)}}{V_{GS(Miller)}}\right) \]

Voltage Rise Time: \[ t_{rv} = \frac{C_{gd} \cdot V_{DS}}{I_g} \]

Total Switching Time: \[ t_{sw} = t_{d(on)} + t_r + t_{fv} + t_{d(off)} + t_{rv} + t_f \]

16. Detailed Power Loss Analysis

MOSFET Losses

Conduction Loss: \[ P_{cond} = I_{D(rms)}^2 \cdot R_{DS(on)} \cdot [1 + \alpha(T_J - 25)] \]

where \(\alpha\) is temperature coefficient (typically 0.004-0.008/°C)

Turn-On Switching Loss: \[ E_{on} = \frac{1}{2} V_{DS} I_D (t_r + t_{fv}) \] \[ P_{sw(on)} = E_{on} \cdot f_{sw} \]

Turn-Off Switching Loss: \[ E_{off} = \frac{1}{2} V_{DS} I_D (t_{rv} + t_f) \] \[ P_{sw(off)} = E_{off} \cdot f_{sw} \]

Diode Reverse Recovery Loss: \[ E_{rr} = \frac{1}{4} V_{DS} I_{RR} t_{rr} \] \[ P_{rr} = E_{rr} \cdot f_{sw} \]

IGBT Losses

Conduction Loss (IGBT): \[ P_{cond} = V_{CE0} \cdot I_{C(avg)} + r_C \cdot I_{C(rms)}^2 \]

where \(V_{CE0}\) is threshold voltage, \(r_C\) is on-state resistance

Tail Current Loss (IGBT): \[ E_{tail} = \frac{1}{2} V_{CE} I_{tail} t_{tail} \]

Thyristor/GTO Losses

Average Power Loss: \[ P_{avg} = V_T I_{avg} + \frac{r_T I_{rms}^2}{2} \]

Loss Minimization Strategies:

Reduce switching frequency (increases conduction loss)
Optimize gate resistance (trade-off: EMI vs losses)
Use devices with lower \(R_{DS(on)}\) or \(V_{CE(sat)}\)
Implement soft-switching techniques (ZVS, ZCS)
Select proper heat sink and cooling method

17. Soft Switching Techniques

Zero Voltage Switching (ZVS)

Resonant Frequency: \[ f_r = \frac{1}{2\pi\sqrt{L_r C_r}} \]

Characteristic Impedance: \[ Z_0 = \sqrt{\frac{L_r}{C_r}} \]

ZVS Condition: \[ Q > Q_{min} = \frac{Q_g V_{DC}}{V_{GS}} \]

Zero Current Switching (ZCS)

Resonant Current: \[ i_r(t) = \frac{V_{DC}}{Z_0} \sin(\omega_r t) \]

Soft Switching Benefits:

Reduced switching losses (50-90% reduction)
Lower EMI and noise
Higher switching frequency possible
Reduced stress on devices
Improved efficiency at light loads

Common Topologies:

Resonant DC-DC converters (LLC, LCC, Series/Parallel)
Phase-shifted full bridge (ZVS)
Quasi-resonant converters
Active clamp circuits

18. Semiconductor Material Properties

Property	Si (Silicon)	SiC (Silicon Carbide)	GaN (Gallium Nitride)
Bandgap Energy (eV)	1.12	3.26	3.39
Electric Field (MV/cm)	0.3	2.5	3.3
Electron Mobility (cm²/V·s)	1400	950	1500-2000
Thermal Conductivity (W/cm·K)	1.5	4.9	1.3
Max Junction Temp (°C)	150-175	200-250	200-250
Relative \(R_{on}\)	1	0.01-0.1	0.01-0.05
Switching Speed	Baseline	3-5× faster	5-10× faster
Cost (Relative)	1×	3-5×	2-4×

Baliga Figure of Merit (BFM): \[ BFM = \frac{\varepsilon_r \mu E_{br}^3}{4\pi^2} \]

Higher BFM indicates better power device performance

Wide Bandgap Advantages:

Higher breakdown voltage for given drift region thickness
Lower on-state resistance
Higher operating temperature
Faster switching capability
Smaller device size for same rating
Higher efficiency in power conversion

19. Application Selection Guide

Power Level vs. Frequency

Device Selection by Application:

High Power, Low Frequency (< 1 kHz): Thyristors, GTOs
High Power, Medium Frequency (1-10 kHz): IGBTs, GTOs
Medium Power, High Frequency (10-100 kHz): IGBTs, Power MOSFETs
Low Power, Very High Frequency (> 100 kHz): Power MOSFETs, GaN
High Efficiency, High Frequency: SiC MOSFETs, GaN HEMTs

Voltage-Current Selection Matrix

Low Voltage (< 200 V)

MOSFETs for switching applications
Schottky diodes for rectification
Low \(R_{DS(on)}\) priority

Medium Voltage (200-1200 V)

IGBTs or MOSFETs depending on frequency
Fast recovery diodes
Balance between switching and conduction

High Voltage (1.2-6.5 kV)

IGBTs for medium frequency
Thyristors for line frequency
Series connection may be needed

Very High Voltage (> 6.5 kV)

Thyristors and GTOs
Series connected IGBTs
HVDC applications

20. Reliability and Failure Modes

Mean Time To Failure (Arrhenius Model): \[ MTTF = A \exp\left(\frac{E_a}{kT_J}\right) \]

where \(E_a\) is activation energy, \(k\) is Boltzmann constant

Junction Temperature Cycling (Coffin-Manson): \[ N_f = C (\Delta T_J)^{-n} \]

where \(N_f\) is number of cycles to failure, \(n \approx 5\)

Common Failure Modes:

Electrical Overstress (EOS): Overvoltage, overcurrent, short circuit
Thermal Fatigue: Bond wire liftoff, solder joint cracking
Electromigration: Metal migration in high current density areas
Gate Oxide Breakdown: Excessive \(V_{GS}\), ESD events
Latch-up (MOSFET/IGBT): Parasitic thyristor activation
dv/dt Induced Turn-on: Displacement current through capacitances

Derating Factor: \[ V_{applied} \leq 0.8 \times V_{rated} \] \[ I_{applied} \leq 0.8 \times I_{rated} \]

Typical 80% derating for reliable operation

Reliability Improvement Practices:

Maintain \(T_J\) well below maximum rating
Minimize temperature cycling amplitude
Use adequate snubber and protection circuits
Implement proper PCB layout (low inductance)
Select components with sufficient margins
Regular thermal imaging and monitoring

Quick Reference Summary

Key Switching Parameters:

\(V_{th}\): Threshold voltage
\(R_{DS(on)}, V_{CE(sat)}\): On-state parameters
\(Q_g\): Total gate charge
\(C_{iss}, C_{oss}\): Input/output capacitances
\(t_{on}, t_{off}\): Switching times
\(E_{on}, E_{off}\): Switching energies

Critical Design Equations:

Total losses: \(P_{total} = P_{cond} + P_{sw}\)
Efficiency: \(\eta = \frac{P_{out}}{P_{out} + P_{loss}}\)
Junction temp: \(T_J = T_A + P_D \theta_{JA}\)
Switching loss: \(P_{sw} = \frac{1}{6}VI(t_{on}+t_{off})f\)

⚡ Golden Rules for Power Electronics:

Always derate devices to 80% of maximum ratings
Keep gate drive loop inductance minimum (< 20 nH)
Use proper snubbers for dv/dt and di/dt protection
Monitor junction temperature - it's the #1 reliability factor
Soft switching reduces losses by 50-90%
Wide bandgap devices enable higher efficiency and density