⚡ Digital Electronics

Quick Revision Guide for EEE Students

1. Number Systems

Base Conversions

Decimal to Binary: Successive division by 2
Binary to Decimal: Σ(bit × 2position)
Decimal to Octal: Successive division by 8
Decimal to Hex: Successive division by 16
Binary-Octal-Hex Quick Conversion:
3 binary bits = 1 octal digit
4 binary bits = 1 hex digit

Binary Arithmetic

1's Complement: Invert all bits
2's Complement: 1's complement + 1
Subtraction: A - B = A + (2's complement of B)

2. Boolean Algebra

Basic Laws

Identity Laws:
A + 0 = A
A · 1 = A
Null Laws:
A + 1 = 1
A · 0 = 0
Idempotent Laws:
A + A = A
A · A = A
Complement Laws:
A + A' = 1
A · A' = 0
(A')' = A
Commutative:
A + B = B + A
A · B = B · A

De Morgan's Theorems

(A + B)' = A' · B'
(A · B)' = A' + B'

Other Important Laws

Associative: A + (B + C) = (A + B) + C
Distributive: A(B + C) = AB + AC
Absorption: A + AB = A, A(A + B) = A
Consensus: AB + A'C + BC = AB + A'C

3. Logic Gates

Basic Gates

A B AND OR NOT A NAND NOR XOR XNOR
000011101
010111010
100101010
111100001
Universal Gates: NAND and NOR gates can implement any Boolean function
XOR: A ⊕ B = A'B + AB'
XNOR: A ⊙ B = AB + A'B' = (A ⊕ B)'

4. Karnaugh Maps (K-Maps)

Purpose: Simplify Boolean expressions visually

K-Map Rules

  • Group 1s in powers of 2 (1, 2, 4, 8, 16...)
  • Groups can overlap
  • Make groups as large as possible
  • Minimize number of groups
  • Groups can wrap around edges

Variable Elimination

2-cell group eliminates 1 variable
4-cell group eliminates 2 variables
8-cell group eliminates 3 variables
16-cell group eliminates 4 variables
Gray Code Ordering: Adjacent cells differ by only 1 bit (00, 01, 11, 10)

5. Combinational Circuits

Multiplexer (MUX)

2n:1 MUX requires n select lines
Output Y = Σ(mi · S combination)
4:1 MUX: Y = S₁'S₀'I₀ + S₁'S₀I₁ + S₁S₀'I₂ + S₁S₀I₃

Demultiplexer (DEMUX)

1:2n DEMUX requires n select lines
Distributes one input to 2n outputs

Encoder

2n inputs → n outputs
Priority Encoder: Encodes highest priority input

Decoder

n inputs → 2n outputs
Each output represents one minterm

Adders

Half Adder:
Sum = A ⊕ B
Carry = A · B

Full Adder:
Sum = A ⊕ B ⊕ Cin
Cout = AB + BCin + ACin = AB + Cin(A ⊕ B)

Subtractors

Half Subtractor:
Diff = A ⊕ B
Borrow = A'B

Full Subtractor:
Diff = A ⊕ B ⊕ Bin
Bout = A'B + A'Bin + BBin

Comparators

A = B: (A ⊙ B) = AB + A'B'
A > B: AB'
A < B: A'B

6. Sequential Circuits

Flip-Flops

SR Flip-Flop

SRQnextState
00QNo Change
010Reset
101Set
11XInvalid
Qnext = S + R'Q

JK Flip-Flop

JKQnextState
00QNo Change
010Reset
101Set
11Q'Toggle
Qnext = JQ' + K'Q

D Flip-Flop

DQnext
00
11
Qnext = D

T Flip-Flop

TQnext
0Q
1Q'
Qnext = T ⊕ Q

Flip-Flop Conversions

JK → T: J = K = T
JK → D: J = D, K = D'
D → T: D = T ⊕ Q
T → D: T = D ⊕ Q

7. Registers and Counters

Shift Registers

  • SISO: Serial In Serial Out
  • SIPO: Serial In Parallel Out
  • PISO: Parallel In Serial Out
  • PIPO: Parallel In Parallel Out

Counters

Modulus: Number of states = 2n
MOD-M Counter: M states (0 to M-1)

Asynchronous (Ripple) Counter

Clock applied to first FF only; output of each FF clocks next FF
Delay: n × tpd (n = number of FFs)

Synchronous Counter

Common clock to all FFs; faster than ripple counter
Delay: tpd (constant)

Ring Counter

Modulus = n (number of FFs)
Only one FF is high at a time

Johnson Counter

Modulus = 2n (twice the number of FFs)
Complemented output fed back

8. Memory Devices

RAM (Random Access Memory)

SRAM: Static RAM (flip-flops, faster, expensive)
DRAM: Dynamic RAM (capacitors, needs refresh, cheaper)

ROM (Read Only Memory)

  • PROM: Programmable ROM (one-time)
  • EPROM: Erasable PROM (UV light erase)
  • EEPROM: Electrically Erasable PROM
  • Flash: Block-erasable EEPROM

Memory Organization

Memory Size = 2m × n
m = address lines (words)
n = data lines (bits per word)

Example: 1K × 8 = 1024 words × 8 bits = 8192 bits

9. A/D and D/A Converters

DAC (Digital to Analog Converter)

Binary Weighted DAC

Vout = -Rf/R × (D₀/2⁰ + D₁/2¹ + ... + Dn/2n) × Vref

R-2R Ladder DAC

Uses only two resistor values: R and 2R
Better than binary weighted (easier to manufacture)

ADC (Analog to Digital Converter)

Types

  • Flash ADC: Fastest, most expensive (2n - 1 comparators)
  • Successive Approximation: Medium speed, most common
  • Dual Slope: Slow but accurate
  • Counter Type: Slowest, simple

Specifications

Resolution: 1/2n or Vref/2n
Step Size: Vref/2n
Conversion Time: Time for one conversion

10. Important Formulas & Concepts

Propagation Delay

tpd = (tpHL + tpLH) / 2
where tpHL = high to low delay
tpLH = low to high delay

Power Dissipation

P = Pstatic + Pdynamic
Pdynamic = C × VDD² × f
Speed-Power Product = tpd × P

Fan-out

Fan-out = IOH(driver) / IIH(load) or IOL(driver) / IIL(load)
(whichever is smaller)

Noise Margins

NMH = VOH(min) - VIH(min)
NML = VIL(max) - VOL(max)

State Machine Design Steps

  1. State diagram
  2. State table
  3. State assignment
  4. Flip-flop excitation table
  5. K-map simplification
  6. Logic circuit implementation

11. Quick Revision Tips

✓ SOP vs POS:
SOP (Sum of Products) = OR of ANDs = Σ minterms
POS (Product of Sums) = AND of ORs = Π maxterms
✓ Canonical Forms:
Minterm: Product where all variables appear once
Maxterm: Sum where all variables appear once
✓ Edge Triggering:
Positive edge: 0 → 1 transition (rising edge)
Negative edge: 1 → 0 transition (falling edge)
✓ Hold Time vs Setup Time:
Setup Time (ts): Data stable BEFORE clock edge
Hold Time (th): Data stable AFTER clock edge
Common IC Numbers:
7400 - NAND gate, 7402 - NOR gate, 7404 - NOT gate
7408 - AND gate, 7432 - OR gate, 7486 - XOR gate
7474 - D FF, 7476 - JK FF, 74138 - 3:8 Decoder
74151 - 8:1 MUX, 7483 - 4-bit Full Adder