By the end of this chapter you should be able to:
- Relate the capacity of a memory to its number of address and data lines, and compute any one of the three from the other two.
- Explain why practical chips decode the address in two dimensions rather than one, and quantify the saving in gates.
- Describe the six-transistor SRAM cell and explain how it is read and written without losing its contents.
- Describe the one-transistor DRAM cell, explain why its read is destructive and why it must be refreshed, and calculate the refresh interval and the overhead it costs.
- Compare mask ROM, PROM, EPROM, EEPROM and Flash by programming mechanism, erase granularity and endurance.
- Define access time and cycle time, read them off a read or write cycle diagram, and work out how many wait states a given processor needs.
- Design a memory of a required size from smaller chips, expanding in the word and bit directions, and draw the address decoder with its address map.
A flip-flop stores one bit, and Chapter 25 assembled eight of them into a register that stores a word. Scaling that idea to the millions of bits a system actually needs would be hopeless if every bit had to have its own wire: a million-bit store built as a million registers would need a million enable lines, and the wiring alone would be larger than the storage. A semiconductor memory solves the problem by making the storage cells as small and as regular as possible and then reaching them through an address — a binary number that a decoder converts into exactly one active line.
That single decision organises the whole subject. It fixes the relationship between capacity and the number of pins on the package, it forces the cell to be shrunk to one or six transistors rather than the dozen or so a flip-flop uses, and it produces the timing specification — access time and cycle time — that decides whether a processor must wait. This chapter works through memory organisation and address decoding with real numbers, examines the static and dynamic cells and the refresh that one of them demands, compares the read-only family from mask ROM to Flash, defines the read and write cycle timing, and finishes by building a larger memory out of smaller chips.
1 Words, Bits and the Address Decoder
A memory is specified as \(W \times m\): \(W\) words of \(m\) bits each. The word is the unit that one address reaches, so a \(4096 \times 8\) memory holds 4096 separate eight-bit values and presents one of them at a time. Because the address must distinguish all \(W\) words, and \(n\) binary lines distinguish \(2^n\) things,
The number of address pins is set by the number of words and the number of data pins by the width of the word. Doubling the capacity by doubling the words costs one address pin; doubling it by widening the word costs \(m\) data pins.
| Organisation | Address lines \(n\) | Data lines \(m\) | Capacity |
|---|---|---|---|
| \(256 \times 8\) | 8 | 8 | 2048 bits = 256 bytes |
| \(1\text{K} \times 4\) | 10 | 4 | 4096 bits |
| \(4\text{K} \times 8\) | 12 | 8 | 32768 bits = 4 kbyte |
| \(16\text{K} \times 8\) | 14 | 8 | 131072 bits = 16 kbyte |
| \(64\text{K} \times 1\) | 16 | 1 | 65536 bits |
| \(1\text{M} \times 16\) | 20 | 16 | 16777216 bits = 2 Mbyte |
The decoder is the interesting part. Chapter 18 built an \(n\)-to-\(2^n\) decoder as \(2^n\) AND gates of \(n\) inputs each, and applied directly to a 4096-word memory that means 4096 gates of twelve inputs, or 49152 gate inputs, on a chip whose entire storage is 32768 cells. The decoder would be larger than the memory.
Real chips therefore decode in two dimensions. The cells are laid out as a square array, half of the address lines select a row and the other half select a column, and the cell at the intersection is the one addressed. For 4096 cells arranged as \(64 \times 64\), six address lines drive a 6-to-64 row decoder and six drive a 6-to-64 column decoder: 128 gates of six inputs, or 768 gate inputs against 49152 — a factor of 64 fewer. The saving grows with the array, which is why every memory die is drawn as a square block with decoders along two of its edges.
Three control pins complete the interface. CS (chip select) enables the whole device and is what makes memory expansion possible; WE (write enable) chooses between reading and writing; and OE (output enable) turns on the tri-state output buffers of Chapter 13 so that many chips can share one data bus with only one of them driving it. All three are normally active low, and a deselected chip both ignores its address lines and releases the data bus.
A RAM package has 14 address pins, 8 data pins, and CS, WE and OE. What is its capacity, and how would the figures change for a \(1\text{M} \times 16\) part?
Fourteen address lines address \(2^{14} = 16384\) words, and eight data lines make each word eight bits, so the organisation is \(16\text{K} \times 8\) and the capacity is \(16384 \times 8 = 131072\) bits, or 16 kbyte. For \(1\text{M} \times 16\): \(1048576 = 2^{20}\), so 20 address lines and 16 data lines, and the capacity is \(1048576 \times 16 = 16777216\) bits — 2 Mbyte from 36 signal pins plus control. That ratio, capacity growing as \(2^n\) while pins grow as \(n\), is the whole reason addressing is worth the decoder.
2 The Static RAM Cell
The cell of a static RAM is the bistable circuit of Chapter 21 stripped to its essentials. Two CMOS inverters are connected in a loop, each driving the other’s input, so that the pair has exactly two stable conditions: node \(Q\) high with \(\bar{Q}\) low, or the reverse. Nothing changes as long as the supply is present, which is what static means. Two further transistors, one on each internal node, connect the cell to a pair of bit lines when the word line is raised. Four transistors for the inverters and two for access give the six-transistor cell.
Reading. Both bit lines are first precharged to the same voltage and left floating. The word line is then raised, and the cell — through whichever access transistor sees a low internal node — begins to pull one bit line down while the other stays put. A sense amplifier detects the resulting difference, of the order of a hundred millivolts, and resolves it into a full logic level. The cell is never overpowered during this, so the read is non-destructive: the value is still there afterwards.
Writing. The write drivers force one bit line high and the other low, and the word line is raised. Now the access transistors must beat the inverter that is holding the cell in its old state, which is a question of relative transistor strength: the access devices are made stronger than the inverter pull-ups so that the cell can be flipped, but weaker than the inverter pull-downs so that a read cannot flip it by accident. Those two inequalities are the cell ratio constraints, and they are why an SRAM cell cannot simply be made from six minimum-size transistors.
The consequences follow from the transistor count. Six transistors per bit is expensive: the \(4096 \times 8\) memory of Figure 27.1 contains 32768 cells and therefore 196608 transistors, six times what the dynamic cell of the next section would need for the same capacity. In exchange the SRAM is fast, needs no refresh, and draws only leakage current while it is not being accessed. That combination is why SRAM is used where speed matters and capacity does not — processor registers, cache memory, and the small on-chip memories of a microcontroller. It remains volatile: remove the supply and both inverters lose their drive, and the stored value with it.
Chapter 21 built the SR latch from two cross-coupled NOR gates, and noted that the feedback, not the gates, is what stores the bit. Take away the set and reset inputs, leaving each gate as a plain inverter, and what remains is a store with no way in or out. The two access transistors put the way in and out back, but as a switched connection to a shared pair of bit lines rather than as dedicated inputs — and that is the whole difference between a flip-flop and a memory cell.
Two practical points follow. Because the only current drawn by an idle cell is leakage, an SRAM can be held in a low-power standby state on a very small supply current, which is why battery-backed SRAM was the usual non-volatile store before Flash. And because the stored node holds only a small charge, a single energetic particle striking the silicon can flip it: this is a soft error, an upset of the data with no damage to the circuit, and it is the reason memories in equipment that must not fail carry the Hamming code of Chapter 4.
3 The Dynamic RAM Cell and Refresh
If the value is stored as charge rather than as a state of a circuit, the cell collapses to one transistor and one capacitor. The capacitor holds the bit — charged for 1, discharged for 0 — and the transistor is a switch that connects it to the bit line when the word line is raised. Nothing holds the charge in place, which is why the memory is called dynamic, and why the price of the small cell is paid in two ways.
The read is destructive. Reading means connecting the cell capacitance \(C_s\), which is around 25 fF, to a bit line whose own capacitance \(C_b\) is around ten times larger because it runs the length of the array. The charge redistributes, and if the bit line was precharged to \(V_{DD}/2\) the resulting voltage is
With \(C_s = 25\) fF, \(C_b = 250\) fF, \(V_{DD} = 1.2\) V and a full cell, this gives 0.6545 V against a precharge of 0.6 V — a swing of only \(+54.5\) mV, and \(-54.5\) mV for a stored zero. A sense amplifier must resolve that, and in doing so it drives the bit line to a full level and writes the value back into the cell, which is the only reason the data survives being read at all.
The charge leaks away. The reverse-biased junction of the access transistor passes a small leakage current, of the order of a picoamp. The cell can tolerate losing about half its stored voltage before the sense amplifier can no longer tell 1 from 0, so the time available is
Fifteen milliseconds at room temperature, and less when the chip is hot, since leakage roughly doubles every ten degrees. Every cell must therefore be read and rewritten — refreshed — within a guaranteed period, and the standard specification is 64 ms.
Refresh is not done cell by cell. Activating one word line reads a whole row into the sense amplifiers, which rewrite every cell in that row, so refreshing costs one row access per row.
A DRAM has 4096 rows, a refresh period of 64 ms and a row cycle time of 60 ns. Find the distributed refresh interval and the fraction of time lost to refreshing.
In distributed refresh one row is refreshed at a time, spread evenly through the period, so a row must be done every
In burst refresh all 4096 rows are done one after another, occupying
during which the memory is unavailable. Either way the total time spent refreshing in each 64 ms window is the same, so the overhead is
Less than four parts in a thousand of the available bandwidth, which is why refresh is a nuisance rather than a disaster. It becomes expensive only when the row count is high and the period short: a part with 8192 rows, a 50 ns row cycle and the same 64 ms period costs 0.64 %, and an early device with 1024 rows, a 120 ns cycle and a 4 ms period cost 3.07 %.
One further economy follows from the square array. Because the row and column addresses are needed at different moments, a DRAM multiplexes them onto the same pins, strobing them in with RAS (row address strobe) and CAS (column address strobe). A \(1\text{M} \times 1\) DRAM therefore has ten address pins rather than twenty, at the cost of two strobes and a longer access.
| SRAM | DRAM | |
|---|---|---|
| Cell | 6 transistors | 1 transistor + 1 capacitor |
| Cells for 32768 bits | 196608 transistors | 32768 transistors and capacitors |
| Read | non-destructive | destructive; restored by the sense amplifier |
| Refresh | none | every row within 64 ms, about 0.4 % overhead |
| Addressing | all lines at once | row and column multiplexed on RAS and CAS |
| Typical use | cache, registers, small on-chip stores | main memory |
4 ROM, PROM, EPROM, EEPROM and Flash
A read-only memory keeps its contents without a supply, and the family is best understood as a sequence of answers to one question: how is the pattern put in, and how much of it can be taken out again?
A mask ROM is programmed during fabrication, by the presence or absence of a connection at each cell. It is the cheapest possible cell and the cheapest possible part in volume, and it cannot be changed at all — a corrected program means a new mask set. A PROM moves the programming to the user by putting a fusible link in every cell; a high current blows the links that must read 0. It is programmed once and is irreversible.
The reprogrammable parts all use the same trick: a floating gate, an extra gate buried in the oxide of a MOS transistor with no electrical connection to anything. Charge placed on it shifts the transistor’s threshold voltage, so that the cell either conducts or does not when it is addressed, and since the gate is surrounded by insulator the charge stays for decades. The three devices differ in how the charge is removed. An EPROM is programmed by hot-electron injection and erased by ultraviolet light through a quartz window, which takes about twenty minutes and erases the entire chip. An EEPROM uses Fowler–Nordheim tunnelling through a very thin oxide in both directions, so it is erased electrically, in circuit, one byte at a time. Flash is an EEPROM that gives up byte erasure in exchange for a much smaller cell: it is erased in blocks, which makes it dense and cheap enough to be the storage of nearly every portable device.
| Device | Programmed by | Erased by | Erase granularity | Write cycles |
|---|---|---|---|---|
| Mask ROM | the fabrication mask | not erasable | — | 0 |
| PROM | blowing fusible links | not erasable | — | 1 |
| EPROM | hot-electron injection | ultraviolet light, ~20 min | whole chip | ~100 |
| EEPROM | tunnelling | electrically, in circuit | one byte | 10⁴–10⁶ |
| Flash | tunnelling or injection | electrically, in circuit | one block | 10⁴–10⁵ |
Whatever the technology, a ROM read is combinational: apply an address and a pattern appears. That makes a \(2^n \times m\) ROM a universal implementation of any \(n\)-input, \(m\)-output combinational function — store the truth table and the addressing does the rest. The BCD-to-seven-segment decoder that Chapter 18 designed with gates becomes a \(16 \times 7\) ROM of 112 bits, with no minimisation required and no difference in speed between an easy function and a hard one. Chapter 28 takes that observation as the starting point for programmable logic.
A circuit takes a 4-bit input and produces three outputs. As gates it needs three separate minimisations and three networks of unpredictable size. As a ROM it needs \(2^4 = 16\) words of 3 bits, that is 48 bits, whatever the three functions happen to be, and the access time is the same for all of them. The price is that the size grows as \(2^n\): a 16-input function would need a 65536-word ROM, so the look-up approach is only economical while \(n\) is small — which is exactly why an FPGA is built from four- or six-input look-up tables rather than one enormous one.
The two Flash architectures are worth distinguishing. NOR Flash connects every cell to a bit line individually, so any word can be read in one access; it is used for program storage, from which a processor executes directly. NAND Flash puts the cells in series strings, which makes the cell much smaller but means the smallest readable unit is a page of several kilobytes; it is used for bulk data storage, where the density matters more than random access.
5 Read and Write Cycle Timing
A memory data sheet is mostly a timing specification, and two of its numbers matter more than the rest.
- Access time \(t_{AA}\) is the delay from a valid address to valid data at the pins. It is what decides whether a processor gets its data in time.
- Cycle time \(t_{RC}\) is the minimum interval between the start of one access and the start of the next. It is what decides bandwidth.
These are not the same number, and the difference catches people out. Cycle time is always at least the access time and is usually longer, because after the data has been delivered the internal bit lines must be precharged again before the next row can be raised. A part quoted at \(t_{AA} = 55\) ns may well have \(t_{RC} = 70\) ns, so the maximum sustained read rate is \(1/70\ \text{ns} = 14.3\) million transfers per second, or 14.3 Mbyte/s on an eight-bit bus — not the \(1/55\ \text{ns}\) that the access time alone would suggest.
In the read cycle the address is applied, CS and OE are taken low, and the outputs leave the high-impedance state and become valid \(t_{AA}\) after the address. The data remains valid until the address changes or OE is released. The write cycle is more delicate, because the memory latches its input on the rising edge of WE. Three constraints must hold: the write pulse must be at least \(t_{WP}\) wide; the input data must be stable for \(t_{DS}\) before that rising edge; and it must remain stable for \(t_{DH}\) after it. These are the setup and hold times of Chapter 21 in another guise, and violating them writes a value that is neither the old one nor the new one.
A processor runs at 100 MHz, so its bus cycle is 10 ns, and it expects read data to be valid at the end of the cycle in which the address was issued. It is connected to the memory above, with \(t_{AA} = 55\) ns. How many wait states are needed?
The data cannot appear until 55 ns after the address, and 55 ns is \(\lceil 55/10 \rceil = 6\) bus cycles. One of those is the cycle the processor already allows, so five extra cycles must be inserted: five wait states. The processor spends six cycles on every read where it had budgeted one, which is exactly the pressure that makes designers put a small, fast SRAM cache between the processor and a large, slow main memory.
Latency is \(t_{AA}\) and bandwidth is \(m/t_{RC}\). A memory can have a poor access time and excellent bandwidth if it can overlap accesses, which is what the burst modes of a modern DRAM exploit: the first word of a burst costs the full row access, and the words after it cost only a column access.
6 Expanding Memory in Words and in Bits
Standard chips rarely come in the size a design needs, so memories are assembled from several of them. There are exactly two directions in which to expand, and a real design usually uses both.
Expansion in the bit direction widens the word. Two \(8\text{K} \times 8\) chips make an \(8\text{K} \times 16\) memory: both receive the same thirteen address lines and the same chip select, and they are enabled together, but one drives \(D_7\)–\(D_0\) and the other \(D_{15}\)–\(D_8\). No decoding is added, because the number of words has not changed.
Expansion in the word direction deepens the memory. Here the chips share the data bus and must therefore never drive it at the same time, so exactly one chip select may be active at once. The low-order address lines go to every chip and the high-order lines drive a decoder whose outputs are the chip selects — which is the reason the decoder of Chapter 18 and the tri-state output of Chapter 13 both exist.
The chip count follows from the two directions together. To build \(W \times m\) from chips of \(w \times b\):
the first factor being the number of banks and the second the number of chips per bank. The decoder needs \(\log_2 (W/w)\) inputs, taken from the most significant address lines.
Design the memory, state the decoder and give the address map.
Chip count. \(4096/1024 = 4\) banks and \(8/4 = 2\) chips per bank, so eight chips in all. Checking the arithmetic: \(8 \times 1024 \times 4 = 32768\) bits, and \(4096 \times 8 = 32768\) bits.
Address split. The system address is 12 bits, \(A_{11}\)–\(A_0\), because \(2^{12} = 4096\). Each chip has 10 address pins, so \(A_9\)–\(A_0\) go to all eight chips and the two remaining lines \(A_{11}A_{10}\) drive a 2-to-4 decoder whose four outputs are the bank selects.
| Bank | \(A_{11}A_{10}\) | Address range (hex) | Decimal | Chips |
|---|---|---|---|---|
| 0 | 00 | 000H – 3FFH | 0 – 1023 | one for \(D_3\)–\(D_0\), one for \(D_7\)–\(D_4\) |
| 1 | 01 | 400H – 7FFH | 1024 – 2047 | as above |
| 2 | 10 | 800H – BFFH | 2048 – 3071 | as above |
| 3 | 11 | C00H – FFFH | 3072 – 4095 | as above |
The pattern is worth reading off the hexadecimal. Each bank spans 1024 addresses, which is 400H, so the ranges start at 000H, 400H, 800H and C00H and each ends 3FFH later. WE and OE go to all eight chips in parallel; only CS is decoded, because only CS decides which chip drives the bus.
The same procedure scales. Building \(16\text{K} \times 8\) from \(4\text{K} \times 8\) chips needs \(16384/4096 = 4\) chips and no expansion in the bit direction at all; each chip takes \(A_{11}\)–\(A_0\) and a 2-to-4 decoder on \(A_{13}A_{12}\) gives the four ranges 0000H–0FFFH, 1000H–1FFFH, 2000H–2FFFH and 3000H–3FFFH. A chip of \(8\text{K}\) words based at 2000H occupies 2000H to 3FFFH, because \(8192 = 2000\)H and the last address is one less than the base plus the size.
One practical warning. If a decoder input is left unconnected instead of being decoded — partial decoding, sometimes done to save a gate — the memory appears at several addresses at once, because the ignored line makes no difference to the selection. The same physical byte then answers to two or more addresses, which is called aliasing. It is harmless if the map is documented and a trap if it is not.
7 Summary and Key Results
| Quantity | Relation | Worked value |
|---|---|---|
| Address lines | \(n = \log_2 W\) | \(4\text{K} \times 8\) needs 12; \(1\text{M} \times 16\) needs 20 |
| Capacity | \(W \times m\) bits | \(4096 \times 8 = 32768\) bits = 4 kbyte |
| Two-dimensional decoding | two \(\tfrac{n}{2}\)-to-\(2^{n/2}\) decoders instead of one | 4096 words: 768 gate inputs instead of 49152 |
| SRAM cell | 6 transistors, bistable, non-destructive read | 32768 bits needs 196608 transistors |
| DRAM cell | 1 transistor + 1 capacitor, destructive read | 25 fF onto a 250 fF bit line gives a \(\pm 54.5\) mV swing |
| Refresh | every row within \(t_{REF}\); interval \(t_{REF}/\text{rows}\) | 4096 rows in 64 ms: one row every 15.625 µs, 0.384 % overhead |
| Access and cycle time | latency \(t_{AA}\); bandwidth \(m/t_{RC}\) | 55 ns and 70 ns give 14.3 Mbyte/s and five wait states at 100 MHz |
| Chip count | \((W/w) \times (m/b)\) | \(4\text{K} \times 8\) from \(1\text{K} \times 4\): \(4 \times 2 = 8\) chips |
8 Common Mistakes
Access time is the latency of one read; cycle time is how soon the next read may begin. Cycle time is longer, because the bit lines must be precharged again before the next word line can be raised. Quoting a bandwidth of \(1/t_{AA}\) overstates a 55 ns/70 ns part by 27 %, and a design that issues addresses every 55 ns will read data that the sense amplifiers have not finished resolving.
In word-direction expansion every chip shares the data bus, so exactly one chip may drive it at any moment. The signal that decides which one is CS, and it is the only signal the address decoder should produce; WE and OE are broadcast to all the chips in parallel. Wiring the decoder to OE while leaving every CS active leaves all the chips partly enabled, and two of them driving the bus at once is a short circuit between output stages, not merely a wrong answer.
A DRAM cell has nothing that restores its charge. Refresh happens only because something — an internal counter in a modern part, an external controller in an older one — issues a row access to every row inside the refresh period. If the bus is monopolised for longer than \(t_{REF}\), or if the refresh counter is not running during a low-power mode, the contents are lost, and the loss is silent: the data reads back as whatever the sense amplifiers resolve from an ambiguous bit line.
9 Chapter Review
1. A memory chip has 13 address pins and 8 data pins. State its organisation and capacity. How many such chips are needed for a \(64\text{K} \times 16\) memory, and how many decoder inputs?
Thirteen address lines give \(2^{13} = 8192\) words, so the chip is \(8\text{K} \times 8\) and holds \(8192 \times 8 = 65536\) bits, or 8 kbyte. For \(64\text{K} \times 16\) the chip count is \((65536/8192) \times (16/8) = 8 \times 2 = 16\) chips, arranged as eight banks of two. The eight banks need a 3-to-8 decoder, so three decoder inputs, taken from \(A_{15}A_{14}A_{13}\); the remaining thirteen lines \(A_{12}\)–\(A_0\) go to every chip. Checking: \(16 \times 65536 = 1048576\) bits, and \(65536 \times 16 = 1048576\) bits.
2. Why is a 4096-word memory decoded as a 64 × 64 array rather than with one 12-to-4096 decoder? Quantify the difference.
A one-dimensional decoder needs one AND gate per word, each with as many inputs as there are address lines: 4096 gates of 12 inputs, which is 49152 gate inputs. Splitting the address into two halves of six bits gives a 6-to-64 row decoder and a 6-to-64 column decoder, 128 gates of 6 inputs, which is 768 gate inputs — a factor of 64 fewer for the same 4096 selections. The cell is chosen by the coincidence of one row line and one column line, and the saving grows as the array does, which is why memory dice are square.
3. A DRAM has 8192 rows and must refresh every row within 64 ms; a row cycle takes 50 ns. Find the distributed refresh interval and the overhead, and say what changes if the part is run hot.
The interval is \(64\ \text{ms}/8192 = 7.8125\ \mu\text{s}\), so a row must be refreshed roughly every eight microseconds. The total refresh time in each window is \(8192 \times 50\ \text{ns} = 409.6\ \mu\text{s}\), giving an overhead of \(409.6\ \mu\text{s}/64\ \text{ms} = 0.64\ \%\). Junction leakage roughly doubles for every ten degrees of junction temperature, so the retention time falls and the specified refresh period must be shortened — commonly halved to 32 ms above 85 °C, which doubles the overhead to 1.28 %.
4. A cell holds 25 fF and is read onto a bit line of 250 fF precharged to \(V_{DD}/2\) with \(V_{DD} = 1.2\) V. Find the bit-line swing for a stored 1 and for a stored 0, and explain why the cell must then be written back.
Charge sharing gives \(V_{BL} = (C_sV_{cell} + C_bV_{DD}/2)/(C_s + C_b)\). For a stored 1, \(V_{cell} = 1.2\) V and \(V_{BL} = (25 \times 1.2 + 250 \times 0.6)/275 = 0.6545\) V, a swing of \(+54.5\) mV. For a stored 0, \(V_{cell} = 0\) and \(V_{BL} = 150/275 = 0.5455\) V, a swing of \(-54.5\) mV. In both cases the cell capacitor has been connected to a much larger capacitance and now sits at about 0.6 V, which is neither a 1 nor a 0 — the read has destroyed the stored value. The sense amplifier resolves the small difference and drives the bit line to a full rail, and because the access transistor is still on, that full level is written back into the cell.
5. Eight \(2\text{K} \times 8\) chips are to form a \(16\text{K} \times 8\) memory starting at address 0000H. Give the decoder and the address range of the fifth chip. What goes wrong if \(A_{13}\) is left out of the decoder?
\(16384/2048 = 8\) banks and \(8/8 = 1\) chip per bank, so eight chips, one per bank. Each chip needs \(\log_2 2048 = 11\) address lines, \(A_{10}\)–\(A_0\), and the three remaining lines \(A_{13}A_{12}A_{11}\) drive a 3-to-8 decoder producing the eight chip selects. Each bank spans 2048 = 800H addresses, so chip 0 covers 0000H–07FFH and the fifth chip, chip 4, is selected by \(A_{13}A_{12}A_{11} = 100\) and covers 2000H–27FFH. Omitting \(A_{13}\) leaves a 2-to-4 decoder driving eight selects, so each output is asserted for two different values of \(A_{13}\): every chip answers to two address ranges 8 kbyte apart, and pairs of chips are enabled together onto the shared data bus, which is a bus conflict rather than merely an aliased map.