Introduction to Digital Electronics

1 Analog and Digital Representation

An analog signal represents a quantity by a voltage or current proportional to it. A thermocouple that produces 41 µV per °C is analog: the information is in the exact value. A digital signal represents a quantity by a group of two-valued symbols. The same temperature might be carried as the twelve-bit pattern 0100 1011 0110, in which no individual wire means anything by itself; read as a binary integer that pattern is 1206, and Section 3 shows how a range and a resolution decide that twelve wires were the right number.

The difference that matters is what happens to an error. Suppose each stage in a chain adds 1 % of noise. After ten analog stages the accumulated error is 3 % if the contributions are independent and 10 % if they are correlated, and nothing downstream can remove it, because the receiving stage has no way to tell signal from noise — both are just voltage. After ten digital stages the error is zero, provided the noise at each input stayed below the threshold that separates the two states. Each gate makes a decision and drives a fresh, full-amplitude output.

This is not an argument that digital is better in every respect. A digital representation of a continuous quantity is always an approximation: twelve bits divide a range into 4096 steps and nothing finer, and that quantisation error is the price paid; Chapter 29 returns to it. The point is only that quantisation error is bounded and known at design time, whereas accumulated analog error is neither.

2 Why Two States Rather Than Ten

Nothing in the argument above requires exactly two states. A circuit with ten distinguishable levels would represent a decimal digit on one wire and need far fewer wires. Such circuits have been built. They are not used, for three reasons.

• Noise tolerance falls as levels are added. Spread \(N\) levels over a supply \(V\) and they sit \(V/(N-1)\) apart, so a receiver tolerates half that gap, \(V/2(N-1)\), before it picks the wrong neighbour. On 5 V, two levels tolerate 2.5 V of interference and ten only 0.28 V — nine times worse.
• Two states match the devices. A transistor makes an excellent switch and a mediocre precision amplifier. Saturated and cut off are states it holds naturally, with no trimming and little sensitivity to temperature or device spread — the very drifts that ten levels would have to be held against.
• Two-valued algebra already existed. Boole published his algebra in 1854, and Shannon showed in 1937 that it describes relay switching networks exactly. A ten-valued logic has no equally simple algebra behind it.

So binary it is, and the cost is more wires. Representing the decimal range 0–999 needs three decimal digits or ten bits. That is the trade the whole industry accepted.

The second reason is worth following, because the history of the subject is the history of that one requirement. The relay came first, the network Shannon analysed, switching in about 10 ms on a coil that takes a watt. The vacuum valve switched a thousand times faster with no moving part; ENIAC, of 1946, used 17,468 of them and drew about 150 kW. The transistor, demonstrated in 1947, did the same work in milliwatts. The integrated circuit — Kilby in 1958, Noyce's planar process the year after — changed not the switch but the cost of adding another one, so that what a designer economises on becomes the package and the pin. Parts came to be classified by how much logic one package holds, in names still in daily use:

The boundaries are conventional, but the trend they record is not: a relay switched in about 10 ms and a present-day gate switches in about 10 ps, a factor of \(10^{9}\). None of that altered a single result in Chapters 5 to 11, because the algebra of a two-valued system does not know what the switch is made of — which is why this course takes the abstraction first and the technology in Part 3.

3 Bits, Bytes and Word Length

One two-valued signal carries one bit — a contraction of "binary digit", coined by J. W. Tukey and made standard by Shannon's 1948 paper. One wire distinguishes two things; two wires distinguish four, since each pattern on the first pairs with either pattern on the second; three distinguish eight; and the doubling gives the counting law the rest of the course uses without comment:

An \(n\)-bit group takes \(2^{n}\) patterns and as an unsigned integer covers 0 to \(2^{n}-1\); conversely, if \(M\) values must be told apart, the word length is \(\log_2 M\) rounded up, since a fraction of a bit cannot be wired.

Groups of bits have names, and the names are not interchangeable. A nibble is four bits, exactly one hexadecimal digit and the reason hexadecimal is convenient at all. A byte is eight bits and therefore 256 patterns, the unit in which memory is addressed in Chapter 27. A word is the width the machine's registers and datapath work in — 8, 16, 32 or 64 bits — a property of a design rather than a universal constant, so it needs a machine attached to it before it means anything.

What a pattern means is a matter of code, not of wires: the same eight lines carry 0 to 255 unsigned, \(-128\) to \(+127\) in two's complement, two BCD digits or one ASCII character, and nothing electrical tells them apart.

The same law answers the question that arises whenever decimal and binary meet: a \(d\)-digit decimal number needs \(n = \lceil 3.32\,d \rceil\) bits, so three digits need ten — \(2^{10} = 1024 \ge 1000\), the figure quoted in the previous section — and a bus of \(k\) address lines reaches \(2^{k}\) locations, the arithmetic behind every memory expansion in Chapter 27.

Chapter 2 then does base conversion properly, Chapter 3 adds signs and the range \(-2^{n-1}\) to \(2^{n-1}-1\), and Chapter 4 covers codes chosen for a property other than arithmetic. All three come before Boolean algebra for one reason: you cannot minimise a function until you can say what its inputs mean.

4 Logic Levels, the Transfer Characteristic and Noise Margin

A gate does not produce or expect ideal 0 V and 5 V, and the levels it does guarantee are read off one curve. Sweep the input of an inverting gate slowly from 0 V to the supply and plot the output against it: that is the voltage transfer characteristic, and everything the gate does at DC is in it.

The curve has three parts. Near either rail the slope is almost zero, so a disturbance on the input produces almost none at the output; between them the gate is a high-gain inverting amplifier whose output crosses the whole range for a small change of input.

Where does LOW stop and HIGH begin? Every manufacturer uses the unity-gain criterion: \(V_{IL}\) is the input at the lower point where the slope is \(-1\), and \(V_{IH}\) the input at the upper such point. Displace an input by \(\Delta V_{in}\) and the output moves by \(|A|\,\Delta V_{in}\), where \(A\) is the local slope: where \(|A| < 1\) the disturbance shrinks and dies away along a chain of gates, and where \(|A| > 1\) it grows. The unity-gain points are the boundary between an input a gate can clean up and one it will amplify into an error — the electrical statement of Section 1's argument. The output levels follow, \(V_{OH}\) measured at the \(V_{IL}\) point and \(V_{OL}\) at the \(V_{IH}\) point under worst-case load.

The data sheet compresses that whole curve into four numbers:

• \(V_{OH}\) — the minimum voltage an output guarantees when driving HIGH;
• \(V_{OL}\) — the maximum it guarantees when driving LOW;
• \(V_{IH}\) — the minimum an input is guaranteed to accept as HIGH;
• \(V_{IL}\) — the maximum an input is guaranteed to accept as LOW.

The margins are the gaps between what the driver promises and what the receiver demands:

A noise margin is the interference that can be added on the wire between two gates before the receiving gate might read it wrongly, and the smaller of the two limits the design.

Compare that with 5 V CMOS, where \(V_{OH(\min)} = 4.44\ \text{V}\), \(V_{IH(\min)} = 3.5\ \text{V}\), \(V_{IL(\max)} = 1.5\ \text{V}\) and \(V_{OL(\max)} = 0.33\ \text{V}\), giving margins of 0.94 V and 1.17 V — three to four times better, and about 40 % of the \(V_{DD}/2\) that a gate of infinite gain driving fully to the rails would achieve. Chapter 12 develops this comparison properly.

5 Positive and Negative Logic

Assigning the symbol 1 to the more positive voltage is a convention, not a law. In positive logic the higher voltage is 1; in negative logic the higher voltage is 0. The same physical circuit therefore implements two different functions depending on which convention the reader applies.

Take a gate whose output is at the low voltage only when both inputs are at the high voltage. Read as positive logic, that is an AND function of the two inputs, inverted — a NAND gate. Read as negative logic, the same electrical behaviour is a NOR gate. Nothing about the silicon changed; only the labels did.

Positive logic is assumed everywhere in this course unless a chapter says otherwise. The convention still matters in practice: active-LOW control signals are ubiquitous, which is why a data sheet writes \(\overline{CS}\) or CS# for a chip select that is asserted by pulling it low.

Two ideas are easily confused here. Negative logic is a global reassignment, in which every signal on the drawing changes meaning together; an active-LOW signal is a local decision about one wire inside an otherwise positive-logic system, usually taken because an output sinks current more comfortably than it sources it. Chapter 10 develops the mixed-logic notation in which a bubble states an assertion level rather than an operation.

6 Propagation Delay, Power and the Speed Limit

No gate responds instantly. The propagation delay \(t_{pd}\), measured between the half-way points of the input and output edges, is the second number — after noise margin — that decides whether a design works. A data sheet quotes it twice, as \(t_{PLH}\) and \(t_{PHL}\), which are rarely equal. The cause of the delay is the load: the output charges the capacitance of the track and of every input hanging on it through a finite on-resistance, so an edge is an \(RC\) exponential rather than a step — and that same charge is where the power goes.

Delays add along a path. A ripple-carry adder of \(n\) stages waits for the carry to cross every stage, so its worst-case delay is proportional to \(n\); Chapter 16 shows how carry-look-ahead breaks that dependence. In a clocked system the longest combinational path between two flip-flops — one-bit memories that all sample together on a clock edge, built in Chapter 21 — sets the shortest usable clock period, and each flip-flop adds two numbers of its own: the delay \(t_{pd(\text{FF})}\) from clock edge to output, and the setup time \(t_{su}\) for which its input must be steady beforehand.

Power is the third parameter, and it trades against the other two. A CMOS gate draws almost no current while it sits in either state, since one of the complementary devices is always off; what it costs is the charge moved when it switches. A full cycle takes \(CV^{2}\) from the supply, half dissipated in the pull-up as the load charges and half in the pull-down as it discharges, so a node switching \(f\) times a second dissipates

Here \(f\) is that node's own switching rate and not the clock frequency, since most nodes change far less often than the clock; Chapter 14 derives the expression and turns the difference into an activity factor.

The three parameters are not independent, and no family optimises all of them: a faster family draws more current, a lower supply saves power quadratically but shrinks the margin, and a bigger transistor drives its load faster while loading the gate before it. Chapter 12 defines the speed–power product, the energy per operation in picojoules — the 250 pJ above is exactly such a figure — which is the fair way to compare families.

7 The Structure of a Digital System, and the Shape of This Course

Every digital system in this course decomposes into two kinds of block, and the distinction organises the rest of the syllabus.

A combinational circuit's output depends only on the inputs applied at that moment. Given the input pattern, the output is fully determined; the circuit has no memory of anything earlier. Chapters 5 to 20 are entirely about combinational circuits — how to express them, how to minimise them, and the standard blocks built from them.

A sequential circuit adds storage, and its output depends on the present inputs and on the stored state left by earlier inputs. That feedback path in Figure 1.4 is the whole difference. Chapters 21 to 26 develop it, from the single latch through to the formal design of a machine with a specified state sequence.

One further convention makes the structure tractable, and almost every circuit in this course obeys it. In a synchronous system a single clock reaches every memory element, so all of them sample at the same instant and the state changes only then. Between two edges the combinational block may settle slowly or glitch on the way and none of it matters, provided it has finished before the next edge — which is what reduces a timing analysis to the single inequality of Section 6.

With those two blocks and one clock, the shape of the course follows. Each part takes an idea from this chapter and makes a subject of it.

1. Part 1, Number Systems and Codes (Chapters 2–4). The word-length arithmetic of Section 3 done properly: base conversion, signed representation, and codes chosen for a property other than arithmetic.
2. Part 2, Combinational Logic and Minimisation (Chapters 5–11). The upper block of Figure 1.4: the gates, the algebra that manipulates them, and three methods of reducing an expression — the motive being the critical path of Section 6 as much as gate count.
3. Part 3, Logic Families (Chapters 12–15). The transfer characteristic, noise margins, delay and power of Sections 4 and 6 measured on real families, and what happens where one drives another.
4. Part 4, Combinational Building Blocks (Chapters 16–20). The same block at a coarser grain — adders, decoders, multiplexers, the arithmetic logic unit — the MSI parts of Section 2.
5. Part 5, Sequential Logic (Chapters 21–26). The memory block and the feedback path: setup and hold times become design constraints, and a word statement becomes a state machine and then gates.
6. Part 6, Memories, Programmable Logic and Converters (Chapters 27–30). Many bits stored and reached by an address, logic configured rather than wired, and the return to the continuous world of Section 1.

Read that list backwards and it is a dependency chain: you cannot describe a state machine in VHDL without knowing what a flip-flop is, nor choose one without the parameters of Part 3, nor design the logic that feeds it without Part 2.

8 Summary and Key Results

9 Common Mistakes

10 Chapter Review