By the end of this chapter you should be able to:
- Compute resolution, step size, full-scale output and quantisation error for a converter of stated word length and reference, and quote the signal-to-quantisation-noise ratio.
- Analyse the binary-weighted-resistor DAC and show, with numbers, why its resistor spread makes it impractical beyond about four bits.
- Derive the R-2R ladder output expression from the repeated 2R ‖ 2R = R result, and state why only two resistor values are needed.
- Explain settling time and the origin of code-transition glitches, and size a deglitching sample-and-hold.
- Compare flash, successive-approximation, dual-slope and sigma-delta ADCs on comparator count, conversion time and resolution.
- Work a successive-approximation conversion cycle by cycle, and derive the dual-slope result showing that it is independent of R, C and the clock and rejects mains interference.
- State the sampling theorem and explain what aliasing does to a signal that violates it.
Everything in the twenty-eight chapters before this one has lived inside a convention: a voltage above some threshold means 1, a voltage below another means 0, and anything in between is somebody else's problem. The convention is what gives digital circuits their immunity to noise, and Chapter 1 argued that this immunity is the whole reason the technology won. But the quantities a real system measures and controls — a thermocouple voltage, a motor current, a microphone's output — are continuous, and so are the quantities it must produce. Something has to stand at the boundary and translate.
The two devices that do it are the digital-to-analogue converter, which is the easier of the pair because a digital word already is a set of weights waiting to be summed, and the analogue-to-digital converter, which is harder because it must search for an answer rather than compute one. This chapter derives both. It starts with the arithmetic that governs every converter — resolution, step size and the error you can never remove — then builds two DAC architectures and shows why only one of them survives past a few bits, and finally works through the four ADC architectures you will meet, including a cycle-by-cycle successive approximation and the derivation that explains why a dual-slope converter is immune both to its own component values and to mains hum.
1 Resolution, Step Size and Quantisation Error
An \(n\)-bit converter works with \(2^n\) distinct codes, from \(00\ldots0\) to \(11\ldots1\). Applied to a reference voltage \(V_{REF}\), those codes divide the reference into \(2^n\) equal intervals, and the width of one interval is the step size or LSB size:
The output for code \(D\) is then \(V_o = D\Delta = V_{REF}\,D/2^{n}\), so the largest output, at \(D = 2^n - 1\), is
A converter never quite reaches its reference: the top code sits one step below it. This is why the full-scale output of a 10 V, 8-bit DAC is 9.9609 V and not 10 V, and why data sheets are careful to say "full scale" rather than "reference".
Resolution is that step expressed as a fraction, usually of full scale: \(1/(2^n - 1)\) if you measure against \(V_{FS}\), or \(1/2^n\) against \(V_{REF}\). The two differ by less than half a percent of themselves at eight bits and are often used interchangeably; what matters is that resolution improves geometrically with word length while cost grows with it.
| \(n\) | Codes \(2^n\) | Step \(\Delta\) with \(V_{REF} = 10\) V | Full scale \(V_{FS}\) | Resolution \(1/(2^n-1)\) |
|---|---|---|---|---|
| 4 | 16 | 625 mV | 9.3750 V | 6.667 % |
| 8 | 256 | 39.0625 mV | 9.9609 V | 0.392 % |
| 10 | 1024 | 9.7656 mV | 9.9902 V | 0.0977 % |
| 12 | 4096 | 2.4414 mV | 9.9976 V | 0.0244 % |
| 16 | 65 536 | 152.588 µV | 9.99985 V | 0.00153 % |
Going the other way, an ADC must represent a continuum by one of \(2^n\) codes, and every input inside a step returns the same code. The difference between the actual input and the value the code stands for is quantisation error. With the comparator thresholds offset by half a step — the usual arrangement — the error lies in \(\pm\Delta/2\), and no amount of care in the electronics removes it: it is a consequence of counting, not of imperfection. Treating it as a random variable uniformly distributed over one step gives its rms value \(\Delta/\sqrt{12}\), and comparing that with the rms of a full-scale sine gives the familiar figure
Each extra bit halves the step and so buys about 6 dB. An 8-bit converter cannot better 49.9 dB, and a 12-bit one cannot better 74.0 dB, however good its components are.
Step size \(\Delta = 10/2^{8} = 10/256 = 39.0625\) mV. Full-scale output \(V_{FS} = 10 \times 255/256 = 9.9609375\) V. The code 10110101 is \(181_{10}\), so the DAC produces \(181 \times 0.0390625 = 7.0703125\) V.
Used as an ADC, an input of 7.085 V lies between \(181\Delta = 7.0703\) V and \(182\Delta = 7.1094\) V, and is nearer the lower, so it returns code 181 with a quantisation error of \(7.085 - 7.0703 = 14.7\) mV — inside the bound \(\Delta/2 = 19.53\) mV. The rms quantisation noise is \(39.0625/\sqrt{12} = 11.28\) mV and the best achievable SNR is \(6.02 \times 8 + 1.76 = 49.9\) dB.
The same 10 V reference at 12 bits gives \(\Delta = 2.4414\) mV, sixteen times finer, at the cost of a reference that must now be stable to better than about 1 mV in 10 V — 0.01 % — if the extra bits are to mean anything.
2 The Binary-Weighted-Resistor DAC
A binary word is already a sum of weighted digits, \(D = \sum_k b_k 2^{k}\), so the most direct DAC simply converts each bit into a current proportional to its weight and adds the currents. Give bit \(b_k\) a switch that connects a resistor either to \(V_{REF}\) or to ground, and make the resistor for bit \(k\) equal to \(2^{\,n-1-k}R\) — that is, \(R\) for the MSB, \(2R\) for the next, and so on up to \(2^{n-1}R\) for the LSB. Because an operational amplifier holds its inverting input at a virtual earth, every switched resistor sees the full \(V_{REF}\) across it whatever the other switches are doing, and the currents add cleanly at the summing node:
With \(R_f = R/2\) the expression collapses to \(V_o = -V_{REF} D / 2^{n}\), the ideal transfer characteristic. The circuit is exact, needs one resistor and one switch per bit, and settles in one amplifier time constant.
It is also, past about four bits, useless. The trouble is the resistor spread: the ratio of the largest resistor to the smallest is \(2^{n-1}\), which is 8:1 at four bits, 128:1 at eight and 2048:1 at twelve. Take \(R = 10\) kΩ and \(V_{REF} = 10\) V. At eight bits the MSB branch is 10 kΩ carrying 1.000 mA and the LSB branch is 1.28 MΩ carrying 7.8125 µA; at twelve bits the LSB resistor is 20.48 MΩ, at which value leakage currents and the amplifier's own input bias current are no longer negligible against the signal.
For the total error to stay within \(\pm\tfrac12\) LSB, i.e. \(V_{FS}/2^{n+1}\), the MSB branch — which carries half of full scale — must be correct to \((1/2^{n+1})/(1/2) = 2^{-n}\) of its own value. At eight bits that is \(1/256 = 0.39\,\%\), so a 10 kΩ resistor must hold 39 Ω; at twelve bits it is 0.024 %, or 2.4 Ω in 10 kΩ. Holding such a tolerance across a 2048:1 range of values, over temperature, in one integrated process, is what cannot be done.
Two further objections matter in practice. Resistors of widely different values track each other badly over temperature, because the large ones are physically different structures on the die, so the ratios drift even if trimmed correct at 25 °C. And each switch has an on-resistance of a few ohms, negligible beside 1.28 MΩ but a 0.05 % error beside 10 kΩ — so the MSB, the bit that matters most, is the bit most damaged. What is needed is a network giving binary weights from resistors that are all nearly the same size.
3 The R-2R Ladder DAC
The R-2R ladder produces binary weighting from resistors of only two values, \(R\) and \(2R\), a spread of 2:1 no matter how many bits the converter has. It works because of one repeated observation about the network's impedance, and the derivation is worth doing carefully because it is the standard examination question.
Number the nodes along the horizontal rail from the far end. At the far end a \(2R\) terminating resistor goes to ground, and the \(2R\) branch of the least significant bit also goes to ground or to \(V_{REF}\) through its switch. Every switch connects its branch either to ground or to a reference, and both are at zero impedance, so for the purpose of computing impedance every \(2R\) branch is grounded. Now look left from the first node: two \(2R\) resistors in parallel,
That \(R\) is in series with the next rail resistor \(R\), giving \(2R\) arriving at the second node — where it meets that node's own \(2R\) branch, and the parallel combination is \(R\) again. The pattern repeats at every node without change, which is the whole trick: looking in any direction from any node, the ladder always presents \(2R\), and any node therefore sees \(R\) to its left.
The consequence for the signal is a clean halving. Consider the current injected by one \(2R\) branch whose switch is thrown to \(V_{REF}\). At its node the current divides between the \(R\) looking one way and the \(R\) looking the other, so exactly half of it proceeds towards the output — and at the next node half of that half proceeds, and so on. A branch \(m\) nodes away from the output therefore contributes \(2^{-m}\) of what it injects. Working through with superposition, the ladder output for an \(n\)-bit word \(D\) is
In the inverting, current-steering arrangement the same analysis gives \(V_o = -V_{REF}(R_f/R)D/2^{n}\), and with \(R_f = R\) the output is \(-V_{REF}D/2^{n}\). Only the sign and the scaling constant differ.
Take \(V_{REF} = 10\) V and \(n = 4\), so \(\Delta = 10/16 = 0.625\) V.
1000= 8: \(V_o = 10 \times 8/16 = 5.000\) V — exactly half scale, as the MSB should give.0100= 4: \(V_o = 10 \times 4/16 = 2.500\) V, half of the MSB's contribution.0001= 1: \(V_o = 10 \times 1/16 = 0.625\) V, which is \(\Delta\).1101= 13: \(V_o = 10 \times 13/16 = 8.125\) V, and \(5.000 + 2.500 + 0.625 = 8.125\) V confirms superposition.
Every resistor in the network is 10 kΩ or 20 kΩ. Extending the same converter to twelve bits adds eight more pairs of the identical two values; the weighted ladder of the previous section would have needed a 20.48 MΩ resistor matched to 0.024 %.
Because only the ratio 2:1 has to be right, an R-2R ladder is easy to make in silicon: each \(2R\) is drawn as two \(R\) units in series, so every resistor on the die is physically identical and they track perfectly with temperature. This is the reason essentially every integrated DAC, and the internal DAC of every successive-approximation ADC, uses a ladder of this kind, in either its resistive or its switched-capacitor form.
4 Settling Time and Glitches
Two dynamic specifications decide whether a DAC that is correct in the steady state is usable at speed.
Settling time is the interval between a code change and the output entering, and staying inside, a band of \(\pm\tfrac12\) LSB about the new value. The band tightens as the resolution rises, so settling time grows with word length even when the circuit does not change. For a single-pole output responding with time constant \(\tau\) to a full-scale step, the error decays as \(V_{FS}e^{-t/\tau}\) and the requirement \(V_{FS}e^{-t/\tau} \le V_{FS}/2^{\,n+1}\) gives
At 8 bits that is \(9\ln 2 = 6.24\tau\); at 12 bits \(13 \ln 2 = 9.01\tau\); at 16 bits \(11.78\tau\). With \(\tau = 100\) ns an 8-bit output settles in 624 ns, so the DAC cannot be updated faster than about 1.6 MHz. Large steps are usually slew-rate limited as well: a 10 V step through an amplifier slewing at 10 V/µs takes 1 µs before exponential settling even begins.
Glitches are a different and more insidious problem, and they are the hazards of Chapter 11 reappearing in analogue clothing. Consider an 8-bit DAC stepping from 01111111 (127) to 10000000 (128), a change of one LSB. Every one of the eight switches changes state. If the MSB switch happens to close a few nanoseconds before the seven lower switches open, the DAC momentarily holds 11111111 and drives almost full scale; if it closes late, the code is momentarily 00000000 and the output falls to zero. Either way a narrow spike of up to half the full-scale range appears in the middle of a one-step transition. Its area, quoted in picovolt-seconds or nanovolt-seconds, is the glitch impulse, and the mid-scale transition is always the worst because it is the code change at which the largest number of switches move at once.
The cure is not to make the switches faster — skew of a few hundred picoseconds is unavoidable — but to hide the transition. A deglitching sample-and-hold is placed after the DAC and put into hold just before the code changes, held through the settling interval, and returned to track once the output is inside its error band. The DAC's misbehaviour then never reaches the load. In audio and video converters, where a periodic glitch appears as a fixed spurious tone or a visible edge artefact, this stage is not optional.
5 Flash and Successive-Approximation ADCs
An ADC cannot compute its answer directly, because the input carries no digits to read; it must compare the input against known levels until the code is pinned down. The architectures differ only in how many comparisons they make and whether they make them at once or one after another.
The flash or parallel converter makes them all simultaneously. A chain of \(2^n\) equal resistors across the reference generates every threshold; a comparator at each tap compares the input against its own threshold; and the resulting thermometer code — a solid column of 1s up to the input level and 0s above it — is converted to binary by a priority encoder of the kind built in Chapter 18. Since the topmost tap needs no comparator, the count is
3 bits need 7 comparators, 4 bits need 15, 8 bits need 255, 10 bits need 1023 and 12 bits need 4095. Two extra bits multiply the comparator count — and with it the die area, the input capacitance and the power — by roughly four.
The pay-off is speed: one comparator delay plus one pass through the encoder, perhaps 8 ns in all, so a flash converter samples at hundreds of megahertz. The penalty is that everything scales exponentially, which is why flash parts are found at six to eight bits and essentially never at twelve. The compromise architectures — pipelined and subranging converters — split the word into two or three smaller flash stages with a DAC and a residue amplifier between them, buying resolution at the cost of a few clocks of latency.
The successive-approximation register (SAR) converter goes to the opposite extreme: one comparator, used \(n\) times. It contains a DAC — an R-2R or switched-capacitor ladder as in Section 3 — driven by a register that the control logic fills in one bit per clock, most significant first. The algorithm is a binary search. Set the bit under test to 1, let the DAC settle, and compare: if the DAC output is still at or below \(V_{IN}\) the bit belongs in the answer and is kept, otherwise it is cleared. Each cycle halves the remaining uncertainty, so \(n\) cycles reduce it from \(V_{REF}\) to \(V_{REF}/2^{n}\), which is one step.
The step is \(\Delta = 5/256 = 19.53125\) mV, and the internal DAC produces \(D\Delta\).
| Cycle | Bit tried | Trial code | \(V_{DAC}\) | Compare with 3.150 V | Decision |
|---|---|---|---|---|---|
| 1 | \(b_7\) | 10000000 = 128 | 2.50000 V | below | keep 1 |
| 2 | \(b_6\) | 11000000 = 192 | 3.75000 V | above | clear 0 |
| 3 | \(b_5\) | 10100000 = 160 | 3.12500 V | below | keep 1 |
| 4 | \(b_4\) | 10110000 = 176 | 3.43750 V | above | clear 0 |
| 5 | \(b_3\) | 10101000 = 168 | 3.28125 V | above | clear 0 |
| 6 | \(b_2\) | 10100100 = 164 | 3.20313 V | above | clear 0 |
| 7 | \(b_1\) | 10100010 = 162 | 3.16406 V | above | clear 0 |
| 8 | \(b_0\) | 10100001 = 161 | 3.14453 V | below | keep 1 |
The result is 10100001 = 161, representing \(161 \times 19.53125\ \text{mV} = 3.14453\) V. The residual error is \(3.150 - 3.14453 = 5.47\) mV, comfortably inside the half-step bound of 9.77 mV. Note how the trials converge: the DAC overshoots at cycle 2 and again at cycles 4 to 7, each time by half as much as before.
Conversion time is exactly \(n\) clock periods and does not depend on the input. At 1 MHz an 8-bit conversion takes 8 µs; a 12-bit SAR clocked at 2 MHz takes \(12/2\ \text{MHz} = 6\) µs, giving a maximum sample rate of about 167 ksps. The input must be held constant throughout, so a SAR converter is always preceded by a sample-and-hold — if the input moved during the search, an early bit decision made on one value would be combined with a late one made on another, and the code would be wrong by far more than an LSB.
6 Dual-Slope and Sigma-Delta Converters
Flash and SAR converters are as accurate as their reference chains and comparators. The dual-slope or integrating converter takes a different route: it makes the answer a ratio of two times, so that most of the circuit's imperfections cancel. It is slow, and it is the architecture inside almost every bench multimeter.
The conversion has two phases. In the first, the unknown input is integrated for a fixed interval \(T_1\), set by counting \(N_1\) clock periods. The integrator output at the end of that phase is
In the second phase the input is disconnected and a reference of the opposite polarity is applied, so the integrator ramps back towards zero at a fixed rate \(V_{REF}/RC\). The counter is restarted and stopped by a comparator when the output crosses zero, having counted \(N_2\) periods in a time \(T_2\). Then
\(R\) and \(C\) have cancelled, and so has \(f_{clk}\). The result depends only on the ratio of two counts and on \(V_{REF}\).
That cancellation is the point. The integrating capacitor may drift with temperature, the resistor may be 5 % out, the clock may be a cheap RC oscillator: all three change both slopes by the same factor, and the ratio is untouched. The only components whose accuracy survives into the answer are the reference and the comparator's offset — which is itself largely cancelled, because the same comparator defines both the start and the end of the run-down. This is how a £15 multimeter reads to four digits.
Phase one integrates \(V_{IN}\) — and everything riding on it. The average of a sinusoid of frequency \(f\) over an interval \(T_1\) is proportional to \(\sin(\pi f T_1)/(\pi f T_1)\), which vanishes whenever \(fT_1\) is a whole number. Choosing \(T_1 = 20\) ms — 2000 counts of a 100 kHz clock — makes \(T_1\) exactly one period of 50 Hz, so 50 Hz interference contributes exactly nothing; \(T_1 = 100\) ms gives five periods of 50 Hz and six of 60 Hz, rejecting both. Even 0.5 Hz off tune, at 50.5 Hz, the rejection is still about 40 dB. No other architecture in this chapter gets that for free.
A 3½-digit display reads 0000 to 1999, so full scale is \(N_1 = 2000\) counts. With a 100 kHz clock, \(T_1 = 2000/100\ \text{kHz} = 20\) ms, one mains period. Choose \(V_{REF} = 2.000\) V, so that \(N_2 = 2000 \times V_{IN}/2.000 = 1000\,V_{IN}\) and the count is the input in millivolts, displayed with no scaling arithmetic at all.
An input of 1.234 V gives \(N_2 = 2000 \times 1.234/2.000 = 1234\) counts, and the display reads 1.234 V. Worst-case conversion time is \(T_1 + T_{2,\max} = 20 + 20 = 40\) ms, so the instrument manages 25 readings per second — which is why a multimeter's display updates two or three times a second and why you cannot use one to watch a transient.
The sigma-delta converter reaches high resolution by a third route: trading speed for bits in software rather than in silicon. A one-bit comparator is clocked at an oversampling ratio many times the Nyquist rate — 64 or 256 times — inside a feedback loop containing an integrator. The loop forces the one-bit output's average to follow the input, and, more importantly, the integrator noise-shapes the quantisation error, pushing most of it out of the signal band to high frequency where a digital decimation filter removes it. That filter also decimates the rate back to the wanted one, so many one-bit samples become one high-resolution sample. A second-order modulator at an oversampling ratio of 64 gains about 15 effective bits over the raw one, which is why 24-bit audio and instrumentation converters are nearly all of this type. The costs are filter latency and a megahertz modulator clock — 48 kHz audio at an OSR of 64 needs 3.072 MHz.
7 Choosing a Converter, and the Sampling Rule
The four architectures do not compete so much as occupy different corners of the speed-resolution plane, and the choice is usually made in a single line of reasoning: how fast is the signal, and how many bits does the measurement actually deserve?
| Architecture | Comparators | Conversion time | Typical resolution | Where it is used |
|---|---|---|---|---|
| Flash (parallel) | \(2^n - 1\); 255 at 8 bits, 4095 at 12 | One comparator + encoder delay, ≈ 8 ns → 125 Msps | 6–8 bits | Oscilloscopes, radio front ends, video |
| Pipelined / subranging | A few small flash stages | One sample per clock, a few clocks of latency | 10–14 bits | Software radio, imaging |
| Successive approximation | 1, used \(n\) times | \(n\) clocks; 6 µs for 12 bits at 2 MHz → 167 ksps | 8–16 bits | Microcontroller ADCs, data acquisition |
| Dual slope | 1 | \(T_1 + T_2 \le 40\) ms → 25 sps | 3½–5½ digits | Multimeters, panel meters, weighing |
| Sigma-delta | 1, clocked at 64–256 × the sample rate | Continuous, with filter latency | 16–24 bits | Audio, strain gauges, temperature |
Two rules of thumb sit behind the table. Conversion time and resolution trade against each other almost linearly in the number of comparisons: flash makes \(2^n - 1\) comparisons at once, SAR makes \(n\) in sequence, dual slope makes up to \(2^{n}\) clock periods' worth in sequence, and the times come out in that order. And no converter is better than its reference: the 6 dB per bit of Section 1 is an upper bound that assumes everything else is perfect.
Finally, sampling. An ADC measures a signal only at instants, and the sampling theorem says that a signal with no energy above \(f_{\max}\) is fully recoverable from samples taken at \(f_s > 2f_{\max}\). Violate it and the reconstruction is not merely degraded but wrong: a component at \(f > f_s/2\) reappears as a lower-frequency one at \(|f - kf_s|\), indistinguishable from a genuine signal there. A 5 kHz tone sampled at 8 kHz comes back as 3 kHz, and no later processing separates the two — which is why every converter input is preceded by an analogue anti-alias filter that removes the offending energy before sampling. The theorem and the reconstruction that follows from it belong to signals and systems; here it is enough that the sample rate is a specification, not a convenience.
8 Summary and Key Results
| Quantity | Expression | Worked value |
|---|---|---|
| Step size (LSB) | \(\Delta = V_{REF}/2^{n}\) | 8 bits, 10 V → 39.0625 mV; 12 bits → 2.4414 mV |
| Full-scale output | \(V_{FS} = V_{REF}(2^{n}-1)/2^{n}\) | 8 bits, 10 V → 9.9609 V, one step short of the reference |
| Quantisation error | \(\pm\Delta/2\); rms \(\Delta/\sqrt{12}\) | 8 bits, 10 V → ±19.53 mV; rms 11.28 mV |
| Best SNR | \(6.02n + 1.76\) dB | 8 bits → 49.9 dB; 12 bits → 74.0 dB |
| Weighted-resistor spread | largest/smallest \(= 2^{\,n-1}\) | 8 bits → 128:1 (10 kΩ to 1.28 MΩ); MSB tolerance 0.39 % |
| R-2R output | \(V_o = V_{REF}D/2^{n}\), two resistor values | 4 bits, 10 V, code 1101 → 8.125 V |
| Settling to ±½ LSB | \(t_s = (n+1)\tau\ln 2\) | 8 bits → 6.24\(\tau\); 12 bits → 9.01\(\tau\) |
| Flash comparators | \(2^{n}-1\) | 8 bits → 255; 10 bits → 1023; 12 bits → 4095 |
| SAR conversion time | \(n\) clock periods | 12 bits at 2 MHz → 6 µs, 167 ksps |
| Dual-slope count | \(N_2 = N_1 V_{IN}/V_{REF}\) | \(N_1 = 2000\), \(V_{REF} = 2.000\) V, 1.234 V → 1234 |
9 Common Mistakes
The reference is divided into \(2^{n}\) steps, not \(2^{n}-1\), because there are \(2^{n}\) codes and the first of them is zero. The step of an 8-bit, 10 V converter is \(10/256 = 39.0625\) mV, and the top code produces \(255 \times 39.0625\ \text{mV} = 9.9609\) V, one step below the reference. Using \(10/255\) gives 39.2157 mV and a full-scale output of exactly 10 V, which no real converter reaches.
Resolution is set by the word length; accuracy is set by the reference, the resistor matching, the comparator offset and the settling. A 16-bit converter working from a reference that drifts 0.1 % is delivering about ten honest bits and six digits of decoration. When a data sheet quotes ±2 LSB integral non-linearity at 12 bits, that is the number to design with, not the 12.
A successive-approximation converter takes \(n\) clock periods to decide \(n\) bits, and every decision is made against the input as it is at that instant. If the input moves during the search, the MSB may be decided on one voltage and the LSB on another, and the resulting code can be wrong by many steps rather than by one. The input must be frozen for the whole conversion, which is what the sample-and-hold is for; a flash converter, deciding everything in one instant, does not need one.
10 Chapter Review
1. A 12-bit DAC has \(V_{REF} = 5.000\) V. Find the step size, the full-scale output, the output for the code \(101000000000\), and the maximum quantisation error of the matching ADC.
The step is \(\Delta = 5.000/2^{12} = 5.000/4096 = 1.2207\) mV. Full scale is \(5.000 \times 4095/4096 = 4.99878\) V. The code \(101000000000_2 = 2560_{10}\), so \(V_o = 2560 \times 1.2207\ \text{mV} = 3.1250\) V — which is \(5.000 \times 2560/4096 = 5/1.6\), a useful check. As an ADC the quantisation error is bounded by \(\pm\Delta/2 = \pm 0.6104\) mV, and the rms quantisation noise is \(\Delta/\sqrt{12} = 0.3524\) mV, giving a best-case SNR of \(6.02 \times 12 + 1.76 = 74.0\) dB.
2. A binary-weighted 6-bit DAC uses \(R = 5\) kΩ for the MSB. What resistor does the LSB need, what tolerance must the MSB resistor hold for ±½ LSB accuracy, and what would both become at 10 bits?
The LSB resistor is \(2^{\,n-1}R = 2^{5} \times 5\ \text{k}\Omega = 32 \times 5 = 160\) kΩ, a spread of 32:1. For the total error to stay within \(\pm\tfrac12\) LSB \(= V_{FS}/2^{7}\), the MSB branch, which carries half of full scale, must be accurate to \((1/2^{7})/(1/2) = 2^{-6} = 1.56\,\%\) — about 78 Ω in 5 kΩ, which is achievable. At 10 bits the LSB resistor becomes \(2^{9} \times 5 = 2.56\) MΩ, a 512:1 spread, and the MSB tolerance tightens to \(2^{-10} = 0.098\,\%\), or 4.9 Ω in 5 kΩ, held across that whole range of values and over temperature. That combination is what makes the weighted ladder impractical and sends the designer to the R-2R network, where the ratio needed is 2:1 at every bit.
3. Show that any node of an R-2R ladder sees \(R\) looking towards the terminated end, and hence that the contribution of each bit is half that of the bit above it.
For impedance purposes every \(2R\) branch is grounded, because its switch connects it either to ground or to a zero-impedance reference. At the terminated end two \(2R\) resistors — the terminator and the LSB branch — appear in parallel: \(2R \parallel 2R = R\). That \(R\) is in series with the next rail resistor \(R\), giving \(2R\) presented at the next node, where it meets that node's own \(2R\) branch and again gives \(2R \parallel 2R = R\). The pattern is self-reproducing, so every node sees \(R\) in that direction. A current injected at a node therefore divides equally between the \(R\) to one side and the \(R\) to the other, so exactly half of it moves one node towards the output; after \(m\) nodes only \(2^{-m}\) survives. Successive bits are thus weighted in a 2:1 ratio, and superposition gives \(V_o = V_{REF}D/2^{n}\).
4. An 8-bit SAR ADC with \(V_{REF} = 5.000\) V converts an input of 1.900 V. Work the first four cycles and state the conversion time at a 500 kHz clock.
The step is \(\Delta = 5/256 = 19.53125\) mV. Cycle 1 tries \(b_7\): code 128 gives \(V_{DAC} = 2.5000\) V, which exceeds 1.900 V, so \(b_7 = 0\). Cycle 2 tries \(b_6\): code 64 gives 1.2500 V, below the input, so \(b_6 = 1\). Cycle 3 tries \(b_5\): code 96 gives 1.8750 V, still below, so \(b_5 = 1\). Cycle 4 tries \(b_4\): code 112 gives 2.1875 V, above, so \(b_4 = 0\). The word so far is \(0110\ldots\) and the uncertainty has fallen from 5 V to 0.3125 V in four cycles, exactly a factor of \(2^4\). The full conversion takes 8 clock periods, so at 500 kHz it needs \(8/500\ \text{kHz} = 16\) µs, a maximum sample rate of 62.5 ksps.
5. A dual-slope ADC integrates for \(N_1 = 1000\) counts from a 50 kHz clock, with \(V_{REF} = 1.000\) V. What is \(T_1\), what count results from an input of 0.640 V, and why does the answer not change if the integrating capacitor is 20 % low?
\(T_1 = N_1/f_{clk} = 1000/50\ \text{kHz} = 20\) ms, which is one period of 50 Hz — so mains hum on the input averages to zero over the run-up and is rejected. The run-down count is \(N_2 = N_1 V_{IN}/V_{REF} = 1000 \times 0.640/1.000 = 640\) counts. The capacitor does not appear in that result: a 20 % low value makes the run-up ramp \(V_1 = V_{IN}T_1/RC\) steeper by 25 %, but it makes the run-down slope \(V_{REF}/RC\) steeper by the same 25 %, and the time taken to return from \(V_1\) to zero is unchanged. Only the ratio of the two slopes matters, and \(RC\) cancels out of it — as does the clock frequency, since both intervals are measured in periods of the same clock.